1. Field of the Invention
The present invention is in the field of memory protection mechanisms for preventing or allowing access to different areas of memory based on a privilege level assigned to the software routine initiating the access.
2. Background Information
Modern computer systems generally have numerous software programs and routines that perform various functions. More specifically, a computer system typically has an operating system, a number of drivers and a number of application programs. Typically, the different routines in a computer system share a variety of resources, such as memory and I/O drivers. The sharing of resources leads to possible interference between different routines. For example, a first routine may write data into a memory area that contains the data of a second routine, which may cause problems for the second routine when it begins or resumes execution. This type of problem may become particularly troublesome in a multi-tasking environment.
Some computer systems implement a memory protection mechanism to reduce interference between different software routines. A memory protection mechanism typically restricts access to selected areas of memory to certain privileged software routines. Memory protection mechanisms provide other benefits, as well. For example, such a mechanism may protect diagnostic information when a software routine crashes, facilitating debugging of the failing routine.
A generic 486 microprocessor has a protection mechanism involving four different privilege levels numbered zero through three, with zero representing the most privileged level and three representing the least privileged level. Each memory segment and each software routine is assigned a privilege level. The protection mechanism monitors memory accesses and implements rules related to those memory accesses. Generally, less privileged software routines are not allowed to access more privileged memory segments. Thus, for example, a software routine with a privilege level of 3 generally cannot access a memory segment with a privilege level of 2. It has been found that having a fixed relationship between the privilege levels and rigid rules regarding access rights reduces the flexibility of systems utilizing processors having protection mechanisms.